In recent years, semiconductor devices having TFTs on an insulating substrate made of glass or the like, such as active-matrix liquid crystal displays using TFTs for driving pixels and image sensors, have been developed.
Generally, TFTs used in these devices are made of a silicon semiconductor in the form of a thin film. Silicon semiconductors in the form of a thin film are roughly classified into amorphous silicon semiconductors (a-Si) and crystalline silicon semiconductors. Amorphous silicon semiconductors are fabricated at relatively low temperatures. In addition, they are relatively easy to manufacture by chemical vapor deposition. Furthermore, they can be easily mass-produced. Therefore, amorphous silicon semiconductors have enjoyed the widest acceptance. However, their physical properties such as conductivity are inferior to those of crystalline silicon semiconductors. In order to obtain higher-speed characteristics from amorphous silicon semiconductors, a method of fabricating TFTs having a crystalline silicon semiconductor must be established and has been keenly sought for.
A known method of obtaining a crystalline silicon semiconductor in the form of a thin film comprises forming an amorphous silicon film and thermally annealing it for a long time so as to crystallize the film. However, this method requires a high annealing temperature exceeding 600.degree. C. Therefore, it is difficult to use a cheap glass substrate. Furthermore, the throughput is low because the annealing time is as long as tens of hours.
A phenomenon capable of solving these problems has been found and disclosed in U.S. application Ser. No. 08/160,908 filed Dec. 3, 1993. In particular, if some kind of metal element is added to a silicon film, the metal element acts as a catalyst, so that crystallization progresses at a lower temperature and more quickly. Such metal elements, or catalytic elements, for promoting crystallization include elements belonging to group VIII of the periodic table, i.e., Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, and Pt, transition elements, i.e., Sc, Ti, V, Cr, Mn, Cu, and Zn. Also, Au and Ag can be used as catalytic elements. Among others, Ni produces especially conspicuous effects.
An example of method of fabricating a TFT, using such a metal element is described now by referring to FIGS. 3(A)-3(D). Corning 7059 glass or other non-alkaline borosilicate glass is used as a substrate 301. Usually, a silicon oxide film having a thickness of 500 to 5000 .ANG., e.g. 2000 .ANG., is formed as an underlying film 302 on the substrate. An amorphous silicon film 303 having a thickness of 200 to 5000 .ANG., e.g., 800 .ANG., is deposited on the underlying film by plasma-assisted CVD (PCVD), low-pressure CVD (LPCVD), or other method.
Then, a very thin film 304 having a catalytic element is uniformly formed by sputtering or other method. Since the thickness of the film containing this catalytic element determines the concentration of the catalytic element contained in the silicon film, the thickness is usually as thin as 5 to 100 .ANG.. Where the film is extremely thin, it does not take the form of a film (FIG. 3(A)).
Then, a protective film 306 is formed of silicon oxide or the like, and an annealing step is carried out. The thickness of the protective film is 100 to 1000 .ANG., e.g., 300 .ANG.. The annealing temperature is 450.degree. to 600.degree. C., e.g., 550.degree. C. The annealing time is 1 to 10 hours, e.g., 4 hours. The amorphous silicon film is crystallized by this annealing step. The crystallized silicon film is patterned to form a silicon film region 305 in the form of an island. This island is used as an active layer of a TFT (FIG. 3(B)).
Thereafter, a gate-insulating film 307 and a gate electrode 308 are formed. Using them as a mask, an impurity is implanted by a known self-aligning process to form a source 309 and a drain 310. To activate the impurity, laser irradiation or thermal annealing is utilized as shown in FIG. 3(C).
Then, an interlayer insulator 311 is formed and contact holes are formed therethrough. Electrodes 312 and 313 are formed for the source and drain. Thus, a TFT is completed (FIG. 3(D)).
In the TFT formed in this way, a catalytic element is uniformly dispersed in the active layer to form energy levels in the semiconductor. Therefore, a leakage current tends to occur at the interface between the drain (source) and channel formation region where an especially high electric field is generated at this interface. That is, where a reverse voltage (i.e., a negative voltage for an N-channel TFT and a positive voltage for a P-channel TFT) is applied to the gate electrode, as the absolute value of the applied voltage is increased, the leakage current between the source and drain increases. Additionally, the threshold voltage of the TFT is increased.